A 32GB DDR5 kit that cost around $95 to $250 in mid-2025 is now running $550 to $650, and some forecasters don't think the ceiling has been hit yet. Dell and Lenovo have both moved to raise hardware prices in response. Buyers who assumed this was a normal supply blip are finding out it isn't. The DDR5 shortage driving these prices has a specific, traceable cause: HBM (high bandwidth memory), the memory format powering AI accelerators, is eating the wafer capacity that used to go to standard DDR5 DRAM.
Fusion Worldwide's Market Research Manager, Andrew Czuczwa, flagged a forecast update that shows this squeeze getting worse before it gets better. Here's the story behind the price spike, in plain terms, and what it means for anyone sourcing DDR4 or DDR5 memory right now.
Past DRAM shortages, like the ones in 2017-2018 and 2021, were cyclical. Manufacturers underbuilt capacity, demand spiked, and supply eventually caught up. What's happening to DDR5 pricing in 2026 doesn't follow that pattern, and the reason is more direct than most coverage of this shortage lets on.
Two sources of demand are surging at the same time, and both trace back to the same root cause. HBM demand is soaring, and because one HBM wafer consumes the equivalent of 3 to 4 standard DDR5 wafers, that growth eats disproportionately into the wafer capacity available for DDR5. At the same time, and separately, DDR5 demand itself is soaring, because the same AI buildout also needs enormous volumes of DDR5 RDIMM modules to fill out the servers surrounding those GPU racks. This isn't just a story about HBM stealing DDR5's capacity. Demand for both is spiking at once, from the same source.
That source is straightforward: nearly every major technology company, along with a growing list of national governments, is racing to build the largest AI data center complexes in the world, and all of them are willing to pay a premium for HBM and DDR5 alike to get there first. Samsung, SK Hynix, and Micron together control roughly 95% of global DRAM production, and all three have deliberately redirected wafer capacity toward HBM memory because AI accelerator customers pay far more for it than PC and phone makers pay for standard DDR memory. That shift is what's rewriting the economics of the DRAM market, turning DDR4 and DDR5 into what's left over after HBM allocation, even as demand for that leftover capacity climbs in its own right. HBM, short for high bandwidth memory, is a type of DRAM built by stacking memory dies vertically and connecting them to a processor through a silicon interposer, instead of laying chips flat on a board the way standard DDR memory does. That stacked design is what gives GPUs and AI accelerators the bandwidth they need, and it's exactly why manufacturers are chasing it even as DDR5 orders pile up behind it.
The numbers show how fast that shift has moved. Industry trackers estimate HBM's share of global DRAM wafers has grown to roughly 23% in 2026, up from about 8% just two years earlier. TrendForce has raised its 2026 global memory market forecast to $889.3 billion, up sharply from its prior estimate, and projects HBM consumption growth exceeding 70% year over year in 2026 alone. On the supply side, SK Hynix has committed over $13 billion to a new Cheongju facility built specifically to assemble, package, and test HBM, on top of the HBM-dedicated fab it already brought online this year, and has said its HBM output for 2025 sold out entirely, even before a string of safety incidents at its Cheongju campus tightened things further.
Buyers feel this on the DDR5 side first. Contract prices have risen sharply quarter over quarter through the first half of 2026, and multiple suppliers have told customers to plan for continued double-digit monthly increases. Some analysts don't expect relief until 2027 or 2028.
Fusion Worldwide's Market Research Manager, Andrew Czuczwa, flagged the forecast update that put a number on this shift:
The math is what makes this worth paying attention to. A 6-exabyte increase in HBM memory demand sounds modest next to a 22-exabyte DDR5 shortfall, until you account for wafer consumption. Because a single HBM wafer uses the equivalent capacity of 3 to 4 standard DDR5 wafers, a relatively small bump in HBM forecasts translates into an outsized hit to DDR5 supply. That ratio lines up with what's being reported industry-wide: HBM dies are described as three to four times larger than commodity DDR5 dies, which is exactly why SK Hynix and its peers are building out dedicated HBM assembly capacity rather than expanding standard DRAM lines.
Part of what's driving the increase in HBM forecasts is the pace of the product roadmap itself. HBM3E, the current production generation, ships in 8-high and 12-high stack configurations, and Micron's 12-high, 36GB HBM3E stack delivers more than 1.2 TB/s of bandwidth per stack. HBM4, the next generation, is ramping through 2026 with a substantial bandwidth increase over HBM3E. Each new generation needs more wafer capacity per bit, because stacking more layers means leaving room for the vertical connections between dies. Every step forward on the HBM roadmap adds more pressure on the DDR5 side.
For buyers, this is an early signal, not a lagging indicator. Forecast revisions like this typically show up in allocation and lead times before they show up in headline prices.
The natural question buyers ask is why manufacturers don't simply build more capacity so both HBM and DDR5 can be produced without a tradeoff. The truth is more specific than "they can't." HBM is built on the same advanced-node DRAM lines used for DDR5, using the same base die process, then stacked and packaged differently to create the wide, high-bandwidth interface AI accelerators need. Because HBM and DDR5 share that upstream capacity, every wafer a manufacturer converts to HBM production is a wafer that isn't making DDR5, even though the two products start from the same kind of line.
Manufacturers are responding by building more capacity, not standing still. Samsung, SK Hynix, and Micron are all investing heavily in new fabs and advanced packaging lines aimed at relieving exactly this bottleneck. The problem for buyers is timing. That new capacity is largely targeted to come online in late 2027 or 2028, not this year or next. Until then, every wafer added to HBM production keeps coming directly out of the DDR5 supply available today, and demand for both is still climbing at the same time. That gap between when the shortage started and when new capacity actually ships is the mechanical reason this cycle doesn't behave like the shorter, cyclical shortages buyers may remember from 2017 or 2021.
AI infrastructure spending doesn't behave like consumer demand. Cloud data centers used to pause DRAM upgrades when prices climbed. That pause doesn't happen anymore, because hyperscaler build-out budgets aren't sensitive to a few quarters of higher memory prices the way a PC refresh cycle is.
That means the pricing behavior buyers are seeing now, rising contract prices even as shipment volumes hold flat, is a signal there's little price elasticity left in this market. Buyers aren't negotiating on price as much as they're competing on who can secure allocation first, a dynamic already playing out in the RDIMM market, where only top-tier accounts are consistently getting fully populated server builds.
For procurement teams, that means:
Fusion Worldwide is an independent distributor with 25 years of supplier relationships across the electronic component supply chain. When primary allocation on DDR4, DDR5, or HBM-adjacent memory runs out, Fusion's trading floor sources through its established network, including manufacturers outside the big three, and every part moves through AS9120B, AS6081, and ISO-certified quality and testing processes before it ships.
If your team is watching lead times stretch or facing allocation limits from your primary suppliers, that's exactly the situation Fusion is built for.