A conversation with Claus Aasholm, Founder of Semiconductor Business Review.
AI has redefined how pricing and supply are determined in the global memory market. What used to be a predictable DRAM cycle, demand rises, pricing increases, supply normalizes, has been upended by infrastructure-driven demand that continues regardless of price.
To understand how this shift is unfolding, Fusion Worldwide’s Market Research Manager, Andrew Czuczwa, sat down with Claus Aasholm, Founder of Semiconductor Business Review and a seasoned analyst of the global semiconductor supply chain. Claus is widely recognized for his in-depth financial and capacity analysis across memory manufacturers, and his research is used across suppliers, OEMs, and investors to anticipate where supply pressure will emerge and how pricing power moves across the memory ecosystem. Andrew complements that perspective with real-time sourcing visibility across thousands of active component searches and quoting behavior from companies responding to tightening supply conditions.
Together, the conversation provides a clear view of how AI infrastructure demand is reshaping memory supply.
For years, DRAM cycles followed a familiar pattern: demand rose, prices climbed, PC and mobile shipments slowed, and capacity rebalanced. That model no longer applies.
“You can’t ignore the AI guys. They’re the ones setting the floor — and increasingly the ceiling too.”
— Claus Aasholm, Founder of Semiconductor Business Review
For procurement teams, that means legacy DRAM buyers are now price-takers, not price-setters.
AI demand is price inelastic, which means it doesn’t pull back when prices rise. Hyperscalers continue buying at scale, anchoring the entire DDR4, DDR5, and HBM (High Bandwidth Memory) pricing structure. This fundamentally changes how memory manufacturers make capacity and pricing decisions.
During the last downcycle, DRAM makers posted negative gross margins and drastically cut CapEx. When pricing recovered, AI filled the demand gap immediately, leaving no buffer for legacy memory segments.
HBM has moved from a niche segment to the center of the DRAM business model. It isn’t just technologically critical for AI accelerators, it’s also significantly more profitable per wafer than commodity DRAM. For suppliers, that makes it the natural allocation priority.
“We saw first HBM3, then HBM3E which is 8 stack high…. now it’s 12 stack high and soon it’s HBM4. And each time we do this, it requires more capacity per bit. There’s only one place to take it from… It’s DDR5.”
— Claus Aasholm, Founder of Semiconductor Business Review
Every new GPU generation drives exponential HBM capacity consumption, forcing wafer allocation away from DDR4 and DDR5. Once this allocation occurs upstream, there’s no quick way to rebalance supply.
DDR4 and DDR5 are no longer strategic priorities for memory makers — they are what remains after HBM allocation. Buyers outside of these priority channels are effectively competing in the residual market.
This shortage isn’t looming, it’s already here. HBM continues to take priority upstream because it’s critical for AI GPUs, carries higher margins, and is significantly more profitable for memory manufacturers than commodity DRAM.
“The foundries and memory houses are clear about their priorities. If they can make more money with HBM, that’s where the silicon goes. It’s rational — just not convenient for buyers.”
— Claus Aasholm, Founder of Semiconductor Business Review
This is not just a current production issue — it’s an investment imbalance. Five years ago, memory represented nearly half of wafer fab equipment spend. Today, it’s closer to one-third.
“The last downcycle burned everyone. No one wants to overbuild. But underbuilding has consequences, too — and now they’re here.”
— Claus Aasholm, Founder of Semiconductor Business Review
DDR4 Scarcity and DDR5 Allocation Are the New Baseline
“We’re not talking about a forecast — we’re living in the shortage already. The question is who has access, not if supply will tighten.”
— Claus Aasholm, Founder of Semiconductor Business Review
The DDR4 shortage is no longer emerging — it’s entrenched. DDR5 allocation is tightly controlled. HBM now drives wafer strategy, hyperscalers set the pricing floor, and NAND is on deck as the next pressure point.
This market rewards speed, visibility, and access. Fusion Worldwide connects buyers with verified global semiconductor supply and provides real-time visibility into DDR4, DDR5, NAND, and HBM inventory and pricing through its E-Commerce platform.
The semiconductor supply chain is no longer defined by boom-and-bust cycles — it’s being structurally reshaped by AI infrastructure build-out.
HBM is the priority. DDR4 is scarce. DDR5 is controlled. NAND may be next. Staying ahead means sourcing smarter and acting faster.
For ongoing insights into memory market dynamics, follow Claus Aasholm and Semiconductor Business Review on LinkedIn and Substack.
To explore the full discussion and context behind these insights, read the complete interview transcript.
Is this another DRAM cycle?
No. This reflects a structural shift anchored by AI-driven demand and profitability-based allocation.
Can new fabs resolve supply constraints quickly?
No. New DRAM capacity typically requires 18 to 24 months to impact availability.
Is DDR5 the next pressure point?
Yes. Allocation-based control is already shaping DDR5 access.
Is NAND at risk of tightening next?
Yes. Underinvestment indicates increasing strain as AI workloads accelerate.
Fusion is a trusted partner in the open market, providing the insight and flexibility needed to navigate ongoing supply challenges. Contact now.